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Design of Request Completion Handler for PCI Express

Niranjan Mamadapur
SDM Institute Of Technology

Shriram P Hegde
SDM Institute Of Technology


PCI Express is the third generation high performance I/O bus used to interconnect peripheral devices in applications such as computing and communication platforms. The first generation buses include the ISA, EISA, VESA, and Micro Channel buses, while the second generation buses include PCI, AGP, and PCI-X. PCI Express is an all-encompassing I/O device interconnect bus that has applications in the mobile, desktop, workstation, server, embedded computing and communication platforms. Request completion handler is the interface operates in between the PCIe master and the PCIe client. It performs the data transactions between the PCIe master and PCIe client. Requests are sent to the client through request completion handler and completions are sent back to the master through the request completion handler. Request completion handler performs the completions for non-posted requests as well as posted requests. The scope of this work involves designing the request completion handler for PCIe, develop coding for simulation and test it.